NXP Semiconductors /QN908XC /SYSCON /PMU_CTRL0

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Interpret as PMU_CTRL0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (MEM0_DIS)MEM0_DIS 0 (MEM1_DIS)MEM1_DIS 0 (MEM2_DIS)MEM2_DIS 0 (MEM3_DIS)MEM3_DIS 0 (MEM4_DIS)MEM4_DIS 0 (MEM5_DIS)MEM5_DIS 0 (MEM6_DIS)MEM6_DIS 0 (MEM7_DIS)MEM7_DIS 0 (MEM8_DIS)MEM8_DIS 0 (MEM9_DIS)MEM9_DIS 0 (BLE_DIS)BLE_DIS 0 (FIR_DIS)FIR_DIS 0 (FSP_DIS)FSP_DIS 0 (ANA_PWRON)MCU_MODE 0 (OSC_INT_EN)OSC_INT_EN 0 (RTC_SEC_WAKEUP_EN)RTC_SEC_WAKEUP_EN 0 (WAKEUP_EN)WAKEUP_EN 0 (PMU_EN)PMU_EN 0 (RETENTION_EN)RETENTION_EN 0 (BOND_EN)BOND_EN

MCU_MODE=ANA_PWRON

Description

power management uinit control register 0

Fields

MEM0_DIS

power down sram memory block 0

MEM1_DIS

power down sram memory block 1

MEM2_DIS

power down sram memory block 2

MEM3_DIS

power down sram memory block 3

MEM4_DIS

power down sram memory block 4

MEM5_DIS

power down sram memory block 5

MEM6_DIS

power down sram memory block 6

MEM7_DIS

power down sram memory block 7

MEM8_DIS

power down sram memory block 8

MEM9_DIS

power down sram memory block 9

BLE_DIS

power down BLE

FIR_DIS

power down FIR buffer

FSP_DIS

power down FSP

MCU_MODE

power control of BG, V2I, VREG_A, VREG_D

0 (ANA_PWRON): power on BG, V2I, VREG_A, VREG_D

1 (ANA_PWROFF): power off BG, V2I, VREG_A, VREG_D

OSC_INT_EN

1 to enable OSC_EN as interrupt and wakeup source

RTC_SEC_WAKEUP_EN

1 to enable RTC interrupt as wakeup source

WAKEUP_EN

1 to enable sleep wake up source

PMU_EN

1 to enable chip power down mode

RETENTION_EN

1 to enable all CPU registers to be retentioned in sleep mode

BOND_EN

1 to enable FSP_BOND_EN bond option

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